Generally, servers have memories with ECC (Error Check and Correct) functions in order to gain a reliability of data. ECC memories have capabilities of detecting and correcting any erroneous 1-bit value of 64 bits (8 bytes) by associating 8-bit (1-byte) error correction data per 64-bit memory. This error is called a correctable ECC error. When 2 bits or more have erroneous values at the same time, the ECC memories can detect the occurrences of the error but may not correct the error. This error is called an uncorrectable ECC error.
When uncorrectable ECC error has occurred, it is necessary to replace the memory. On the other hand, when correctable ECC error has occurred, the data can be corrected, but when correctable ECC error has occurred multiple times, the quality of the memory is questionable. Thus, the memory needs to be replaced when correctable ECC error has occurred a certain number of times or more. That is, when the number of occurrences of correctable ECC error is greater than or equal to a certain number, it is desired that the error is handled as hardware error. Therefore, the number of occurrences of error provides important information for detecting hardware error, particularly, a memory defect.
One example of related art is disclosed in Japanese Laid-open Patent Publication No. 2-244339 (refer to claim 1 and FIG. 1 therein). In the related art, during occurrence of memory error, hardware operates to cause a CPU to execute a trap program for error processing by causing software to generate a trap each time memory error occurs, i.e., to interrupt a CPU each time memory error occurs. Thus, there is a problem in that a correct number of occurrences of memory error may not be known when error occurs sequentially.